16*16 limited intermediate buffer switch module for ATM networks
Anil Kumar Gupta, L.O. Barbosa, N.D. Georganas · 2002
An investigation is made of the performance of a nonblocking packet switch having input buffers and a limited amount of buffers within the switch fabric, where contention for the output ports occurs. This technique improves the performance significantly, while maintaining the switch fabric speed equal to that of the port speed. For uniform traffic, a 16*16 switch with head of line priority scheduling has an achievable throughput equal to 87.5%. The simulation results suggest that for unbalanced and bursty traffic, the performance of the switch does not degrade appreciably.>