Executing compressed programs on an embedded RISC architecture
Andrew Wolfe, Alex Chanin · ACM SIGMICRO newsletter/SIGMICRO newsletter/SIGMICRO, TCMICRO newsletter · 1992
The difference in code size between RISC and CISC processors appears to be a significant factor limiting the use of RISC architectures in embedded systems.Fortunately, RISC programs can be effectively compressed.An ideal solution is to design a RISC system that can directly execute compressed programs.A new RISC system architecture called a Compressed Code RISC Processor is presented.This processor depends on a code-expanding instruction cache to manage compressed programs.The compression is transparent to the processor since all instructions are executed from cache.Experimental simulations show that a significant degree of compression can be achieved from a fixed encoding scheme.The impact on system performance is slight and for some memory implementations the reduced memory bandwidth actually increases performance.