1.5 V operation sector-erasable flash memory with BIpolar Transistor Selected (BITS) P-channel cells
T. Ohnakado, N. Ajika, Hirokazu Hayashi, Hiroshi Takada, K. Kobayashi, Kengo Sugahara, Shin-ichi SATOH, Hirokazu Miyoshi · 2002
A novel BIpolar Transistor Selected (BITS) P-channel flash memory cell is proposed and a very low 1.5 V non-WL (word line)-boosting read and sector-erase operations are successfully achieved. Moveover, this cell technology not only maintains the advantages of the P-channel DINOR (DIvided bit line NOR) flash memory, but also realizes the amplification of cell current, which is favorable for fast access operation.