Area-time-power efficient VLSI design for residue-to-binary converter based on moduli set (2n,2n+1−1,2n−1)
Su-Hon Lin, Ming‐Hwa Sheu, Chao-Hsiang Wang, Yuan-Ching Kuo · 2008
The moduli set M1=(2n,2n+1−1,2n−1) which is free of 2a+1 modulus is profitable to construct a high-speed residue number system (RNS). In this paper, we derive a reduced-complexity residue-to-binary conversion algorithm for M1by using New Chinese Remainder Theorem (CRT). The resulting converter architecture mainly consists of carry-save adders (CSAs), modular adders and multiplexer (MUX) which is suitable for an efficient VLSI implementation. Under the same dynamic range (DR) requirement, the proposed converter design is significantly more efficient than the latest design for M1with respect to Area-Time (AT), Time-Power (TP) and Area-Time-Power (ATP) products. Based on UMC 0.18um CMOS cell-based technology, the chip area for 16-bit residue-to-binary converter is only 931“931um2and the working frequency is 135MHz.