A 1 GOPS reconfigurable signal processing IC with embedded FPGA and 3-port 1.2 GB/s flash memory subsystem
Michele Borgatti, L. Call, G. De Sandre, B. Forêt, D. Iezzi, Francesco Lertora, G. Muzzi, Marco Pasotti, M. Poles, Pier Luigi Rolandi · 2003
A 1 GOPS dynamically reconfigurable processing unit with embedded flash memory and SRAM-based FPGA for image/voice processing/recognition applications is described. Code, data and FPGA bitstreams are stored in the embedded flash memory and are independently accessible through 3 content-specific, 64 b I/O ports with a peak read rate of 1.2 GB/s. The system is implemented in a 0.18 /spl mu/m 2P 6M CMOS flash technology with a chip area of 70 mm/sup 2/.