Resistorless Bi-CMOS logic circuit
H. Javan, H. Chamas · 2002
A logic circuit design which combines bipolar emitter coupled logic (ECL) and CMOS technology with extremely low power consumption and low propagation delay is introduced. The calculated and the simulated results show that the power-speed product is 12.5 P-J which is 35 P-J less than the conventional Motorola ECL-10 k. Simulated results show that the proper operation of the circuit requires an optimum bias of 1.5 V. The corresponding maximum peak transient power is 17 mW, while the maximum RMS power is about 10 mW.>