Implementation of Wave-Pipelined Interconnects in FPGAs
Terrence Mak, Crescenzo D’Alessandro, Pete Sedcole, Peter Y. K. Cheung, Alex Yakovlev, Wayne W. Luk · 2008
Global interconnection and communication at high clock frequencies are becoming more problematic in FPGA. In this paper, we address this problem by presenting an interconnect wave-pipelining strategy, which utilizes the existing programmable interconnects fabrics to provide high-throughput communication in FPGA. Two design approaches for interconnect wave-pipelining, using simple clock phase shifting and asynchronous phase encoding, are presented in this paper. Experimental results from a Xilinx Virtex-5 FPGA device are also presented.