System-Level Verification Platform using System Verilog Layered Testbench & SystemC OOP
Young-Jin Oh, Gi-Yong Song · International Journal of Control and Automation · 2014
Systems have recently performed multiple functions through a combination of several IPs. SystemVerilog has useful components for modeling and verification at System-level. The OOP of SysemVerilog supports only single inheritance in a verification environment based on a layered testbench of SystemVerilog. It is restricted to construct environment verification. SystemC is a language for system level design at multiple abstraction levels and supports multiple inheritance. We adopt SystemC to design components of a verification platform which employ multiple inheritance, and combine it with the SystemVerilog-based verification platform using SystemVerilog DPI and the ModelSim macro in this paper. Employing the multiple inheritance of SystemC makes the design of a verification environment simple and easy through code reusability. Another characteristic of OOP with SystemVerilog and SystemC is that it can create a reconfigurable verification platform.