Architecture and Software Implementation of HDTV Video Decoder on a Singlechip, MPEG Decoder
Yuanjiu Li Yuhuang Ye · 2006
This paper presents the architecture and software design of HDTV video decoder on a 200-MHz single-chip microprocessor. First, the paper analyzes the hardware architecture of video decoder system on this MPEG decoder and describes the function of each module in this system, including the PES Parser, Decode pipeline, SC Analyzer, and Display Processor. Then it gives the software control and implementation of this video decoder. This video decoder meets the requirements for MPEG-2 MP@HL real-time decoding. The outcome of this paper should be helpful to the design of HDTV Set Top Box.