A modular bit-serial architecture for large-constraint-length Viterbi decoding
M.A. Bree, David E. Dodds, R.J. Bolton, S. Kumar, Brian L. F. Daku · IEEE Journal of Solid-State Circuits · 1992
A node-parallel Viterbi decoding architecture and bit-serial processing and communication are presented. An important aspect of this structure is that short-constraint-length decoders may be interconnected, without loss of throughput, to implement a Viterbi decoder of larger constraint length. The convolutional encoder trellis is modeled by appropriate wiring of decoder processing nodes: a variety of generating codes can be accommodated. Bit-serial communication links between nodes require only a single wire each and thus interconnection area is relatively small. During each decoding cycle, more than 50 b need to be communicated on each serial link and thus the technique is limited to moderate bit rate applications. A constraint length K=4 'proof of concept' chip was developed using 9860 transistors in 3 mu m CMOS on a 4.51-mm*4.51-mm die size. The complete circuit operates at 280 kb/s and supports any rate 1/2 or 1/3 code with eight-level soft decision.>