Scalable, sub-1W, sub-10ps clock skew, global clock distribution architecture for Intel® Core™ i7/i5/i3 microprocessors
Guru Shamanna, Nasser A. Kurd, Jonathan Douglas, Matthew Morrise · 2010
This paper describes global clock distribution architecture of Intel®Core™i7/i5/i3 microprocessor family. Highlight of this paper is a pseudo-recombinant clock distribution architecture successfully implemented in 32nm/45nm generation of Core™i7/i5/i3 processors. This clock distribution topology achieves less than 10ps clock skew while consuming a maximum power of 1 Watt across entire operating voltage and frequency range.