On-line delay testing of digital circuits
P. Franco, Edward J. McCluskey · 2002
A new technique for on-line checking of digital systems is proposed. It is shown that, under certain timing restrictions, an off-line delay-fault testing method called Stability Checking can be used for on-line checking. Efficient CMOS on-line Stability Checker designs are presented, and an algorithm for meeting timing restrictions is described. Benchmark results are shown. On-line Stability Checkers detect errors caused by most common reliability failures and transients, and are shown to perform almost as well as duplication at a fraction of the hardware cost. Since outputs are checked independently, good diagnosability is possible.>