A self-learning neural network chip with 125 neurons and 10 K self-organization synapses
Yutaka Arima, Kazuki Mashiko, Keisuke Okada, TAIJI YAMADA, Akira Maeda, Harufusa Kondoh, Shinsuke Kayano · IEEE Journal of Solid-State Circuits · 1991
A learning neural network LSI chip is described. The chip integrates 125 neuron units and 10K synapse units with the 1.0 mu m double-poly-Si, double-metal CMOS technology. Most of this integration has been realized by using a mixed design architecture of digital and analog circuits. The fully feedback connection network LSI can memorize at least 15 patterns with 50 mu s learning time for each pattern. Under the condition that each test vector keeps a Hamming distance of 6 from memorized pattern, a correct association rate of 98% is obtained. The relaxation time is 1 to 2 mu s. This chip consumes less than 7.5 W.>