Design of a Hierarchy-Bus Based MPSoC on FPGA
Wei Zhang, Gaoming Du, Yi Wei Xu, Minglun Gao, Luo-Feng Geng, Bing Zhang, Zhao-yu Jiang, Ning Hou, Yi-hua Tang · 2006
The increasing system resources available on field-programmable gate arrays (FPGA) enable the integration of complex system on one programmable chip. This paper focuses on the design and implementation of a hierarchy-bus based multi-processor system-on-chip (MPSoC) integrating 4 ARM processors on FPGA. Experimental results had been obtained running at 60MHz with total area requiring 34% adaptive look-up tables (ALUTs) of Altera Stratix II EP2S180 and a maxim performance speedup of 3.2