An efficient algorithm for single and multiple fault test sets generation
Sailendra Nath Banerjee, Ranajit Kishore Thakur, Pramode Ranjan Bhattacharjee · International Journal of Computer Mathematics · 1985
A direct approach for single and multiple fault test set generation on any number of lines of a logical circuit has been described in this paper. The present paper simplifies the results of Ku and Masson [2] for which only some visual inspections are needed rather than going through tedious steps of algebraic manipulations. This method is thus easily applicable to arbitrarily large combinational circuits, whether it is fan-out free or with fan-out nodes.