A video delay line compiler
Frédéric Rothan, C. Joanblanq, P. Senn · 2002
A digital delay line compiler is described. Depending on the number of bits per word, the delay required, and the operating frequency, the compiler automatically generates the layout of the block, including output and input buffers and registers for synchronization. The implementation is independent of basic cell characteristics. The architecture is described, as well as the method used for area optimization. Experimental results are discussed.>