Sparse FIR filters and the impact on FPGA area usage
Sean G. Patronis, Linda S. DeBrunner · 2008
In FIR filter design, a sparse filter is one that has a majority of zeros for coefficients. Generally, a sparse filter is designed in order to save area and speed up computations, but when implementing a sparse filter in an FPGA the expected area savings may not be realized. This paper shows that sparsity in an FIR filter does not generally translate directly into FPGA space (area) savings on a Virtex-4 FPGA.