Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB Standard
A.C. Dam, M.G.J. Lammertink, Kenneth C. Rovers, J. Slagman, A.M. Wellink · 2006
This paper addresses the implementation of Reed-Solomon decoding for battery-powered wireless devices. The scope of this paper is constrained by the digital media broadcasting (DMB). The most critical element of the Reed-Solomon algorithm is implemented on two different reconfigurable hardware architectures: an FPGA and a coarse-grained architecture: the Montium, The remaining parts are executed on an ARM processor. The results of this research show that a co-design of the ARM together with an FPGA or a Montium leads to a substantial decrease in energy consumption. The energy consumption of syndrome calculation of the Reed-Solomon decoding algorithm is estimated for an FPGA and a Montium by means of simulations. The Montium proves to be more efficient