Design of a real time image compression system using multiple DSP 56000/96000 processors
Swaminathan Srinivasan, Elwin Chandra Monie, Giri Prasad · 2002
An image compression system has been implemented using DSP 56000/96000 family of processors. Block processing is done on image data of 8/spl times/8 size to reduce I/O overheads. The coding scheme uses Discrete Cosine Transform (DCT) followed by a Llyod-Max quantizer. A multiprocessor system using these processors has also been designed for compression of 512/spl times/512 images in real time.>