Low Power Probabilistic Floating Point Multiplier Design
Aman Gupta, Satyam Mandavalli, Vincent John Mooney III, Keck Voon Ling, Arindam Basu, Henry Johan, Budianto Tandianus · 2011
We present a low power probabilistic floating point multiplier. Probabilistic computation has been shown to be a technique for achieving energy efficient designs. As best known to the authors, this is the first attempt to use probabilistic digital logic to attain low power in a floating point multiplier. To validate the approach, probabilistic multiplications are introduced in a ray tracing algorithm used in computer graphics applications. It is then shown that energy savings of around 31% can be achieved in a ray tracing algorithm's floating point multipliers with negligible degradation in the perceptual quality of the generated image.