NeuroFPGA-implementing artificial neural networks on programmable logic devices
Daniel Ferrer, Ramiro González, Roberto Fleitas, Julio Pérez Acle, Rafael M. Canetti · LA Referencia (Red Federada de Repositorios Institucionales de Publicaciones Científicas) · 2004
An FPGA implementation of a multilayer perceptron neural network is presented. The system is parameterized both in network related aspects (e.g.: number of layers and number of neurons in each layer) and implementation parameters (e.g.: word width, pre-scaling factors and number of available multipliers). This allows to use the design for different network realizations, or to try different area-speed trade-offs simply by recompiling the design. Fixed point arithmetic with pre-scaling configurable in a per layer basis was used. The system was tested on an ARC-PCI board from altera/spl trade/ several examples from different application domains were implemented showing the flexibility and ease of use of the obtained circuit. Even with the rather old board used, an appreciable speed-up was obtained compared with a software-only implementation based on Matlab neural network toolbox.