Parallel Symbol Architectures for H.264/AVC Binary Coder Based on Arithmetic Coding
Grzegorz Pastuszak · 2006
The number of clock cycles sacrificed to process binary symbols in hardware entropy coders may limit the performance of the whole H.264/AVC coder. This paper describes enhancements of the architecture based on the parallel symbol encoding. Five versions of the architecture are described to study the area/performance trade-off. The implementation results show that the parallel symbol encoding allows higher efficiency expressed as the area/performance ratio