A 439K gates/10.9KB SRAM/2–328 mW dual mode video decoder supporting temporal/spatial scalable video
Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jiun-In Guo, Jiawei Chen, Jinn-Shan Wang, Chin-Hsien Wang, Hsiang-Hui Huang, Ching-Hwa Cheng · 2009
The first dual mode video decoder with 4-level temporal/spatial scalability and 32/64-bit adjustable memory bus width is proposed. A design automation environment of simulation and verification is established to automatically verify the correctness and completeness of the proposed design. Using a 0.13 ¿m CMOS technology, it comprises 439 K gates/10.9 KB SRAM and consumes 2~328 mW in decoding CIF~HD1080 videos at 3.75~30 fps when operating at 1~150 MHz, respectively.