A BIST scheme based on resistance match for current-mode R-2R ladder Digital-to-Analog Converter
Yuan Jun, Tachibana Masayoshi · 2011
This paper presents a Built-in Self-Test (BIST) scheme and its implementation for a current-mode R-2R ladder Digital-to-Analog Converter (DAC). The technique is based on the resistance match of the R-2R ladder in DAC. With the extra Design for Testability (DFT) circuits, test constant current follows into two resistance-matched branches, and the voltage drops on two branches of the resistor ladder change the voltage values at the inputs of the operational amplifier, which works as a comparator in the test mode. The output of the operational amplifier is employed for fault detection through a window comparator, which creates a pass/fail signature signal. The circuit-level simulation and experimental results of the BIST system for a 8-bit DAC in standard CMOS 0.18-µm technology are presented to demonstrate the feasibility of the proposed BIST scheme with fault coverage of 96% and area overhead of approximately 6%.