Multithreaded coprocessor interface for multi-core multimedia SoC
Shih-Hao Ou, Tay–Jyi Lin, Xiang Sheng Deng, Zhi Hong Zhuo, Chih Wei Liu · Asia and South Pacific Design Automation Conference · 2008
Modern architectures exploit task level parallelism to improve their performance in a cost-effective manner. However, task synchronization and management is time consuming and wastes computing resources especially on application-specific architectures, such as DSP. In this paper, we propose a smart coprocessor interface that helps to offload the task management job from MPU or DSP. In our simulations, our approach can improve the overall performance of a dual-core platform by 57%. The hardware overhead of the interface is only 1.56% of the DSP core.