A partitioning approach to improve reconfigurable neuron-inspired online BIST
Ali Shahabi, S. Behdad Hosseini, Hassan Sohofi, Zainalabedin Navabi · 2010
Two of the most challenging issues in online testing are deriving a general tester scheme for various circuits and reducing the area overhead. This paper presents a novel reconfigurable online tester using artificial neural networks to test combinational hardware. Our proposed BIST architecture has the capability of testing a number of arbitrary sub-modules of a big design simultaneously by time-multiplexing between them. Output partitioning method is proposed as a powerful technique to reduce neural network training time and the tester area overhead. Our experimental results show that after proper partitioning the average area overhead is reduced by 16% in data-path and 33% in memory area. Also average fault detection latency has been improved by 14%.