A learning multiple-valued logic network: algebra, algorithm, and applications
Zheng Tang, Qiping Cao, Okihiko Ishizuka · IEEE Transactions on Computers · 1998
We propose a multiple valued logic (MVL) network with functional completeness and develop its learning capability. The MVL network consists of layered arithmetic piecewise linear processors. Since the arithmetic operations of the network are basically a wired sum and a piecewise linear operation, their implementations should be rather simple and straightforward. Furthermore, the MVL network can be trained by the traditional backpropagation algorithm directly. The algorithm trains the networks using examples and appears to be available for most MVL problems of interest.