PowerPC/sup (TM)/ array verification methodology using formal techniques
N. Ganguly, Magdy S. Abadir, M. Pandey · 2002
In this paper we discuss the methodology used on PowerPC RISC microprocessors to verify the correctness of embedded array blocks. The functional behavior of these blocks cannot be verified using traditional functional simulators since the search space is too large. Our methodology combines the use of equivalence checking formal methods, simulation using ATPG test vectors, and symbolic trajectory evaluation We discuss how these techniques are applied to verify the operation of an array in during design representation formats. We also discuss how these techniques can be used for checking the consistency of different design representations.