An FPGA-based floating-point processor array supporting a high-precision dot product
Fritz Mayer-Lindenberg, Valerij Beller · 2006
This note reports on the design of a pipelined floating point processor on a Spartan-III FPGA. It is implemented as a coprocessor to a novel, universal controller for pipelined data path designs that provides a high-level API and compiler support for general FPGA applications. The controller adds multithreading and networking to the processor design, and the option of SIMD processing. The complexity issue of high precision floating point in an FPGA implementation is taken care of by efficiently implementing a recent algorithm of Rump that computes the dot product of two vectors at the same level of precision as a double precision processor yet using single precision operations only including a few non-standard primitives. For these special operations, our FPGA based processor actually outperforms hardwired floating-point DSP chips performing them in software. Through the inclusion of sequential control and networking our design provides a realistic estimate of the floating point system performance of FPGA in standard applications