A multi-standard video accelerator based on a vector architecture
V.A. Chouliaras, Jose Luis Nunez-Yanez, David J. Mulvaney, Fabrizio S. Rovati, Daniele Alfonso · IEEE Transactions on Consumer Electronics · 2005
A multi-standard video encoding coprocessor is presented that efficiently accelerates MPEG-2, MPEG-4 (XViD) and a proprietary H.264 encoder. The proposed architecture attaches to a configurable, extensible RISC CPU to form a highly efficient solution to the computational complexity of current and emerging video coding standards. A subset of the ISA has been implemented as a VLSI macrocell for a high performance 0.13 /spl mu/m silicon process.