A method for the efficient development of timed and untimed transaction-level models of systems-on-chip
Jérôme Cornet, Florence Maraninchi, Laurent Maillet-Contoz · 2008
Transaction Level Modeling (TLM) captures abstract models of Systems-on-Chip that simulate faster than traditional RTL simulations and are available earlier in the design flow. Such models allow the development of the embedded software on a virtual prototype of the hardware, before the chip is available. Various levels of details in TL models are needed; using untimed and timed models for different purposes is a usual practice.