Verification techniques for deadlock and real time constraint violation
Bouraoui Ouni, N. Sayadi, Abdellatif Mtibaa, Abdelkrim Zitouni, Mohamed Nadhir Abid · 2004
Summary form only given. Design automation depends on high-level modelling and system specification. Such modelling and specification requires a long time. Therefore designers need to introduce verification techniques in order to avoid several problems in codesign. We present two verification techniques based on the discrete event model (DE) in order to allow the automatic verification of deadlock and real time constraint violation.