An effective BIST scheme for Booth multipliers
Dimitris Gizopoulos, Antonis Paschalis, Y. Zorian · 2002
Booth multipliers are widely used in both general purpose datapath structures and specialized Digital Signal Processors. Such multipliers when embedded in complex ICs have low controllability and observability, so the use of a suitable BIST scheme is a necessity. No Such BIST schemes for Booth multipliers are available to our knowledge in the open literature. A very effective BIST scheme for Booth multipliers is introduced. The algorithmic BIST patterns that this scheme generates guarantee >99% fault coverage. The required Test Pattern Generator consists of a simple fixed-size binary counter or maximum length LFSR, independent of the site of the multiplier. Several count-based compaction schemes are evaluated and a new such compaction scheme is found to be the most effective. The novel BIST scheme is generic, i.e., independent of specific implementations of the multiplier cells and does not require DFT in the multiplier design. Due to its effectiveness and regularity this BIST architecture was adopted for automatic BIST synthesis via the parameterized multiplier generation tool.