Multi-Rate QC-LDPC Encoder
Huxing Zhang, Hongyang Yu · 2009
A multi-rate memory-efficient encoder for low-density parity-check (LDPC) codes is proposed in this paper based on shift-register-adder-accumulator (SRAA). The SRAA algorithm simplifies the encoder computation module and reduces the complexity of the operation. The LDPC code generator matrix is constructed by lots of quasi-cyclic square matrices in the Chinese digital TV terrestrial broadcasting standard (DMB-T), and the encoder is presented based on the quasi-cyclic character that reduces the memory cost. Simulations demonstrate that the proposed encoder can satisfy the DMB-T in three-rate according to different bit-rate option with lower complexity.