Commercial design verification: methodology and tools
Carl Pixley, N.R. Strader, William C. Bruce, Jaehong Park, Matt Kaufmann, Kurt Shultz, Michael L Burns, Jayanand Asok Kumar, Jun Tang Yuan, Jen-Yee Nguyen · 2002
Commercial design verification is a complex activity involving many abstraction levels (such as architectural, register transfer, gate, switch, circuit, fabrication), many different aspects of design (such as timing, speed, functional, power, reliability and manufacturability) and many different design styles (such as ASIC, full custom, semi-custom, memory, cores, and asynchronous). We present a representative design flow and methodology that is common to many commercial integrated circuit design environments and that concentrates on functional validation using informal verification (e.g., simulation, emulation and ATPG) and formal verification (e.g., logic checking and sequential verification).