Redundant binary based fixed-point divider
Abderrahmane Bennis, Monte P. Tull · 2006
This paper describes a new high-performance divider for binary fixed-point numbers. The divider is based on the Goldschmidt iterative algorithm and uses redundant binary number encoding of the dividend and divisor to provide improved performance for each iteration. Both redundant binary conversion and redundant binary multiplier circuit details are described. Further, the divider design unrolls the Goldschmidt iterations into a combinational clockless circuit, thereby yielding minimal latency in redundant binary quotient generation while providing opportunities for pipelining. Included in the design are normalization circuits for the binary divider inputs. Results are given for Xilinx FPGA implementations and show a 24% performance increase over previous designs.