Architectural and Functional optimizations to the Digital subsystem of Active Digital Aura (ADA) chip
Jayant Kumar · 2015
The primary objective of this thesis project is to investigate and develop optimal software and hardware architectures to detect the Start Of Packet (SOP) indicator present in a Body Coupled Communication (BCC) based message packet. The SOP detection module is a part of the receiver block present in the digital subsystem of the Active Digital Aura (ADA) circuit [2]. The project is comprised of two tasks. The first task is to investigate alternative solutions to detect the SOP in a received message. Accurate detection of the SOP under varying noise conditions is crucial for reducing retransmissions and improve the data rate. The various investigated solutions are implemented using VHDL and tested for the accuracy of SOP detection using Xilinx ISE simulations. The solutions are also synthesized using Cadence Synthesis tools to determine the hardware statistics such as area utilization, power consumption, and slack. The solution having highest accuracy and optimal hardware resource utilization is chosen as the best possible alternative solution. Furthermore, to verify the SOP detection in a typical BCC scenario, different types of noise such as burst noise and distributed noise with varying intensity are injected to the message packet to introduce errors. Both the current and best alternative solutions are subjected to functionality tests under these noise variations to determine the detection accuracy and limitations of each. The second task is to incorporate necessary modifications to the digital subsystem of existing ADA circuit [2] to develop a prototype model of it on the ML401 (Xilinx Virtex-4 based) FPGA board [3]. The prototype aids in testing of the modifications made to the digital subsystem of ADA chip (such as the SOP detection module) at real time, prior to ASIC manufacturing. A firmware application is also developed for an ARM Cortex-M4F based ?C device (host) which is used to interact with and test the FPGA prototype. The functionality of the existing and alternate SOP detection solutions are verified at real time on the FPGA hardware.