ON THE TESTABLE DESIGN OF BILATERAL BIT-LEVEL SYSTOLIC ARRAYS
S. Bandyopadhyay, Bhargab B. Bhattacharya · 2005
This paper presents a new testable design scheme appli- cable to any arbitrary 1-dimensional bilateral systolic array. The hardware overhead is a global control he and a small amount of additional logic per cell . The proposed design ensures that all cells in the array can simultaneously be set to any state in constant steps after initialization, regardless of the size of the array. The design also supports propaga- tion of test outcomes to observable exiremitles so that the where IVI is the number of states per cell and N is the number