Fault Tolerant Memories Based on Expander Graphs
Shashi Kiran Chilappagari, Bane V. Vasic · 2007
In this paper we consider memories built from components subject to transient faults. We propose a fault-tolerant memory architecture based on LDPC codes and show the existence of memories which can tolerate constant fraction of failures in all the components. Our proof relies on the expansion property of the underlying Tanner graph of the code. We illustrate our results with specific numerical examples.