An algorithm for the allocation of functional units from realistic RT component libraries
Roger Ang, Nikil D. Dutt · 1994
Existing algorithms in High-Level Synthesis (HLS) typically assume a direct mapping of hardware description language (HDL) operators to RT units. This assumption simplifies synthesis to generic RT components, but prevents effective use of complex databook components, custom designed cells, previously synthesized RT modules, and RT module generators. In this paper, we present an algorithm for allocation in HLS for reuse of existing RT-level components. This approach can be used to customize HLS tools to user-specific RT libraries. Our experiments show improvements of 10--37% in area over conventional approaches. 1 Introduction Most approaches towards high-level synthesis (HLS) of synchronous circuits from hardware description languages (HDLs) assume a simple scheme for mapping behavioral operators to register-transfer (RT) components. Synthesis tools often assume an abstract HDL operator directly maps to a single RT operation which in turn can be performed by a few generic components....