Mapping switch-level simulation onto gate-level hardware accelerators
Alok Kumar Jain, Randal E. Bryant · 1991
In this paper, we present a framework for performing switchlevel simulation on hardware accelerators.A symbolic analyzer preprocesses the MOS network into a functionally equivalent Boolean representation.The analyzer thus converts switch-level simulation into a task of evaluating Boolean expressions.Our approach maps the Boolean representation into the instruction set of the hardware accelerator.The resultant framework supports switch level simulation on a class of hardware accelerators that traditionally have been limited to gate-level simulation.1.