Cache Consistency in Hierarchical-Ring-Based Multiprocessors
Keith Farkas, Zvonko Vranesic, Michael Stumm · 1992
A cache consistency scheme is presented for a class of multiprocessors based on a hierarchy of rings. By taking advantage of the natural broadcast and ordering properties of rings, cache consistency is achieved via a simple, selective-broadcast based protocol requiring no complex hardware. Using address-trace driven simulations of the Hector shared-memory multiprocessor, it is shown that the scheme performs well. 1 Introduction The design of cache consistency protocols for largescale shared-memory multiprocessors is complicated because of several factors. First, due to limited bandwidth of a single bus, large-scale multiprocessors have more complex interconnection networks. These networks use split-cycle protocols and allow concurrent memory accesses. In some cases these networks are not race-free [13], which makes it difficult to impose a global ordering on accesses. The second complication pertains to the increased potential for contention at some of the system nodes such as network...