Encoded arithmetic for reversible logic
Akhilesh Tyagi · 2002
The CCD based implementations of reversible logic consume a constant amount of energy per switching event which depends only on the charge packet size and not on the interconnect length. Within this model of computation, it seems possible to leverage data, encoding to reduce the number of switching events for the computation, resulting in lower overall computation energy. We explore the applicability of encoding for different datapath functions. We also develop a lower bound on switching count in a model similar to the traditional VLSI model of computation. A notion of reversible communication complexity is also developed.>