An FPGA-based infant monitoring system
Patrick Dickinson, K. Appiah, Andrew Hunter, S. Ormston · 2006
We have designed an automated visual surveillance system for monitoring sleeping infants. The low-level image processing is implemented on an embedded Xilinx's Virtex II XC2v6000 FPGA and quantifies the level of scene activity using a specially designed background subtraction algorithm. We present our algorithm and show how we have optimised it for this platform.