Multiplier‐less VLSI architectures for radix‐22folded pipelined complex FFT core
Abhishek Mankar, N Prasad, Ansuman DiptiSankar Das, Sukadev Meher · International Journal of Circuit Theory and Applications · 2014
Summary The advantages of a multiplier‐less architecture are reduction in hardware and latency. This paper proposes multiplier‐less architectures for the implementation of radix‐22folded pipelined complex FFT core based on coordinate rotation digital computer (CORDIC) and new distributed arithmetic (NEDA). The number of points considered in the work is sixteen and the folding is done by a factor of four. The proposed designs have been implemented on Xilinx XC5VSX240T‐2FF1738 FPGA and also have been synthesized using the Synopsys design compiler. Proposed designs based on NEDA have reduced area over 83% and based on CORDIC have a reduced area over 78%. The observed slice‐delay product for NEDA based designs are 2.196 and 5.735, and for CORDIC based design is 2.369. Copyright © 2014 John Wiley & Sons, Ltd.