Observation time reduction for IDDQ testing of bridging faults in sequential circuits
Yoshinobu Higami, Kewal K. Saluja, K. Kinoshita · 2002
One of the major unsolved and ignored but significant problems is the reduction of the long testing time for IDDQ testing of CMOS circuits. Since IDDQ must be observed after dynamic current disappears, testing time is much longer than logic testing. This paper presents a method to reduce the observation time for IDDQ testing. The proposed method is a static method which focuses on selection of vectors to be observed instead of removing vectors. Experimental results are presented to demonstrate the effectiveness of the proposed method.