LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology
Junwhan Ahn, Ki‐Young Choi · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2013
This brief presents an approach to reduce static power consumption in peripheral circuits of spin-transfer torque RAM (STT-RAM) instruction caches. It is based on the key observation that only a small set of instructions is accessed inside a program loop. We propose to add a small static RAM cache called loop cache between the processor and the L1 instruction cache made of STT-RAM. When the loop cache has an entire loop cached, the L1 instruction cache can be turned off to save energy during the execution of the loop. Experimental results show that the proposed approach achieves 49% reduction in energy consumption over the STT-RAM baseline.