Rapid implementation of DSP algorithms for algorithm evaluation: a decimation filter example
Pasin Israsena, Sitthipong Wongnamkum · 2008
This paper discuses a design flow that integrates the developments of DSP algorithms and FPGA hardware to increase performance and reduce development time. A decimation filter for analog-to-digital conversion is implemented as an example, with the results analyzed and compared to the more conventional RTL coding and synthesis approach.