Dynamic Partial Reconfiguration Through Ethernet Link
Daniel Llamocca, Marios S. Pattichis, Alonzo Vera, James Lyke · AIAA Infotech@Aerospace 2010 · 2010
YNAMIC Partial Reconfiguration is a technique that allows a portion of the FPGA to be reprogrammed while the rest of the device keeps working, and as such, it offers enormous possibilities for adaptive systems. The usual design flow involves storing the pre-generated partial bitstreams on a flash memory for its further streaming to the FPGA configuration port. Our approach consists of getting rid of the slow and capacity-limited flash memory by streaming the reconfiguration data through the Ethernet link, which places no restrictions on the number and size of bitstream files as well as the time at which the bitstreams are generated. More importantly, it offers the possibility of programming the FPGA from a remote location, i.e. remote dynamic partial reconfiguration. We present a proof-ofconcept system that includes software routines on the server side (PC) and client side (processor inside the FPGA), as well as an image processing hardware core used both to verify the correctness of the output data and to provide actual measurements. We obtain an Ethernet link speed of 12Mbps (only payload) and a dynamic partial reconfiguration speed of 26.24 Mbps. This system provides evidence that remote dynamic partial reconfiguration is a viable technology that takes the inherent flexibility of dynamic partial reconfiguration even further.