ATLAS: a chip-multiprocessor with transactional memory support
Njuguna Njoroge, Jared Casper, Sewook Wee, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun · 2007
Chip-multiprocessors are quickly becoming popular in embedded systems. However, the practical success of CMPs strongly depends on addressing the difficulty of multi-threaded application development for such systems. Trans-actional Memory (TM) promises to simplify concurrency management in multithreaded applications by allowing pro-grammers to specify coarse-grain parallel tasks, while achieving performance comparable to fine-grain lock-based applications. This paper presents ATLAS, the first prototype of a CMP with hardware support for transactional memory. AT-LAS includes 8 embedded PowerPC cores that access co-herent shared memory in a transactional manner. The data cache for each core is modified to support the speculative buffering and conflict detection necessary for transactional execution. We have mapped ATLAS to the BEE2 multi-FPGA board to create a full-system prototype that operates at 100MHz, boots Linux, and provides significant perfor-mance and ease-of-use benefits for a range of parallel ap-plications. Overall, the ATLAS prototype provides an ex-cellent framework for further research on the software and hardware techniques necessary to deliver on the potential of transactional memory. 1